The existing Influence Maximization (IM) algorithms of social network have the problem of low influence range caused by only selecting local optimal nodes at present. In order to solve the problem, considering the propagation advantage of core node and structure hole node, a maximization algorithm based on Structure Hole and Degree Discount (SHDD) was proposd. Firstly, the ideas of structure hole and centrality degree were integrated and applied to the influence maximization problem, and the factor α combining the structure hole node and the core node was found out to play the maximum propagation function, which made the information spread more widely to increase the influence of the whole network. Then, in order to highlight the advantages of the integration of two ideas, the influence of second-degree neighbor was added to the evaluation criteria of structure hole to select the structure hole node. The experimental results on data sets of different scales show that, compared with DegreeDiscount algorithm, SHDD can increase the influence range without consuming too much time, and compared with the Structure-based Greedy (SG) algorithm, SHDD can expand the influence range and reduce the time cost in the network with large clustering coefficient. The proposed SHDD algorithm can maximize the advantages of structure hole node and core node fusion when factor α is 0.6, and it can expand the influence range more steadily in the social network with large clustering coefficient.

Due to the increasingly high performance requirements on the Advanced Encryption Standard (AES) algorithm which was widely used, software-based cryptographic algorithms have been increasingly difficult to meet the demands of high-throughput ciper cracking. As a result, more and more encryption algorithms have been accelerated by using Field-Programmable Gate Array (FPGA) platform. Focused on the issue that the development of AES algorithm based on FPGA has high complexity and long development cycle, with High-Level Synthesis (HLS) design methodologies, AES hardware acceleration algorithm was designed by using high-level programming language. Firstly, loop unrolling, etc were used to improve operation parallelism. Secondly, to make full use of on-chip memory and circuit resources, the resource balance optimization technology was used. Finally, the full pipeline structure was added to improve the clock frequency and throughput of the overall design. The detailed analysis and comparison of the benchmark design and different optimized designs with structural expansion, resource balance and pipeline were decribed. The experimental results show that the clock frequency of AES algorithm is up to 127.06 MHz and the throughput eventually achieves 16.26 Gb/s on Xilinx xc7z020clg484 platform, compared with the benchmark AES design, performance increases by three orders of magnitude.